1. Field of the Invention
This invention relates to the field of high-speed comparator circuits.
2. Background Art
In data recovery circuits, phase lock loops are utilized to lock onto timing pulses encoded in the data to be recovered to facilitate synchronized data extraction. An integral part of the phase lock loop is a voltage-controlled oscillator (VCO). The linear response of the VCO is a requirement for a stable phase lock loop.
In an all-CMOS VCO implementation, it is difficult to achieve a linear response at high frequency operation. The non-linearity at high frequency is caused by intrinsic delays within the circuit. An all-CMOS VCO is described in the copending U.S. patent application Ser. No. 07/960,534, filed Oct. 13, 1992, assigned to the present assignee, entitled "Linearized and Delay Compensated All-CMOS VCO." A block diagram of an all-CMOS VCO is illustrated in FIG. 1.
Transconductance converter block 101 receives control voltage Vin 100 and provides control currents 113 and 130. These currents are proportional to the control voltage Vin. Control current (I) 130 is provided to VCO core block 202. VCO core block 202 has two output nodes, 217 and 218, that are coupled to a positive voltage supply through capacitors 203 and 204, respectively. Nodes 217 and 218 alternate between two operational states with one node being in a first state while the other node is in the second state. In the first operational state, the output node is charged to the positive voltage supply value and maintains that value until the operational state has changed. In the second operational state, the output node ramps down from the positive voltage supply value at a rate determined by control current 130 (I), until a change of state is triggered. VCO core 202 receives clk+input 215 and clk-input 216 to control the state switching of the output nodes 217 and 218. Output nodes 217 and 218 are coupled to the negative input of comparators 205 and 206, respectively. A trip voltage is provided to the positive inputs of comparators 205 and 206 on line 225. Comparators 205 and 206 are coupled to the "set" and "reset" inputs, respectively, of set/reset flip-flop 207. S-R flip-flop (latch) 207 provides Q and Q* outputs which represent clk+215 and clk-216 output signals, respectively. Signals 215 and 216 represent the oscillating output of the voltage-controlled oscillator system.
When node 217 is in the ramp down state and reaches the trip voltage value, comparator 205 outputs a high pulse to the set input of latch 207. This causes the output of latch 207 (Q, Q*), to change states from (0, 1) to (1, 0). The clk+ and clk- signals then cause the VCO core 202 to switch the operational states of output nodes 217 and 218. When node 218 ramps down past the trip voltage value, comparator 206 triggers the reset input of latch 207 and causes the output to change state from (1, 0) to (0, 1) causing clk+ and clk- to trigger another cycle.
The half cycle of this VCO block is ideally the time it takes for the ramp voltage to drop from the positive voltage supply value to the trip voltage value. However, once the ramp voltage crosses the trip voltage value, the ramp voltage continues to drop until the comparator and latch can switch the VCO core. Thus, the half cycle of the VCO is the sum of the ramp down time plus the comparator/latch delay. Therefore, the frequency response of this VCO circuit (without the compensation loop) is: ##EQU1## where V is the potential difference between the supply voltage and the trip voltage values, C is the capacitance of capacitors 203 and 204, I is control current 130, and delv is the comparator/latch delay. Thus, the delay of the comparator and latch introduce non-linearity to the frequency-versus-voltage response at high frequencies where the ideal half cycle term CV/I is of the same order of magnitude as the comparator/latch delay delv.
A graph illustrating the frequency versus voltage characteristics of the VCO is illustrated in FIG. 2. The solid line represents the ideal frequency response of the VCO in which the frequency is only a function of the ramp down time of the VCO core (F.sub.OUT =1/(2T.sub.H)). The dashed curve is the uncompensated output of the VCO, which flattens out toward the dashed limit line that is equivalent to F.sub.OUT =1/(2 delv). A phase lock loop, utilizing a VCO with the frequency response described by the dashed curve, cannot be analyzed and may be unstable and/or unable to lock in phase to i this reason, it is desired to minimize the effect of the comparator/latch delay in the VCO circuit.
A prior art CMOS comparator is disclosed in "A 30 MHz Low-Jitter, High-Linearity CMOS Voltage-Controlled Oscillator," by Wakayama and Abidi in the IEEE Journal of Solid State Electronics, Vol. SC-22, No. 6, December, 1987, pp. 1074-1080. The comparator of Wakayama, et al., is illustrated in FIG. 3.
A PMOS transistor M5 is coupled between a positive voltage supply and node 300, with its gate coupled to a negative voltage supply. PMOS transistor M1 is coupled between node 300 and the negative voltage supply, with its gate acting as the positive input terminal 304. PMOS transistor M2 is coupled between node 300 and output node 303, with its gate acting as negative input terminal 306. NMOS transistor M4 is coupled between output node 303 and the negative supply voltage, with its gate coupled to high-impedance node HIZ 302. NMOS transistor M3 is coupled between high impedance node 302 and the negative voltage supply, with its gate coupled to output node 303. NMOS transistor M6 is coupled between output node 303 and the negative voltage supply, with its gate acting as a reset RST input 301.
The comparator of FIG. 3 is referred to as a "positive feedback" comparator. Transistors M3 and M4 are cross-coupled, and therefore transistor M4 should not be strongly turned on. HIZ 302 should have enough voltage to allow transistor M4 to sink one-half the current flowing through transistor M1 when transistor M2 is off. As IN- voltage crosses the IN+ voltage, the current passing through transistor M2 becomes larger than the current passing through transistor M4, the voltage at output node OUT 303 begins to rise and transistor M3 turns on. HIZ node 302 is pulled low via transistor M3, and transistor M4 begins to shut down. The positive feedback takes over and OUT 303 node latches high. The voltage vs. time characteristics of this circuit are shown in FIG. 4.
Lines 410 and 411 on FIG. 4(A) illustrate voltage vs. time characteristics of IN+ and IN- as would occur if this comparator were used in the VCO described above. IN+ represents a stable reference voltage and IN- represents the ramping voltage. IN+ is constant at a voltage VTRIP. Prior to time T1, IN- is stable at a voltage VPOS. At time T1, IN- begins to ramp downwards at a constant rate. At time T2, IN- crosses IN+. At time T6, IN- is charged back up to voltage VPOS.
Lines 412 and 413 of FIG. 4(B) illustrate the voltage vs. time characteristics for HIZ input node 302 and output node 303. Prior to time T3, HIZ node 302 maintains a constant voltage VBIAS generated by external circuitry, and OUT node 303 maintains a voltage consistent with the negative voltage supply value. At time T3, triggered by the crossing of IN- under IN+, OUT begins to rise toward VPOS and transistor M3 begins to turn on pulling HIZ 302 toward the negative voltage supply value. At time T4, HIZ input 302 has been pulled to the negative voltage supply value and transistor M4 has been turned off, causing the output voltage at OUT node 303 to charge rapidly up to VPOS, which it reaches at time T5. At time T6, when IN- crosses back over IN+, the voltage at output node 303 remains at the voltage VPOS because the positive feedback maintains transistor M4 in a high impedance state. At time T7, reset signal RST 301 is asserted by external circuitry (line 414 of FIG. 4(C)). With signal RST asserted, transistor M6 becomes a low impedance path between the output node 303 and the negative voltage supply, thus discharging output node 303. As the output voltage drops toward the negative voltage supply, the impedance of transistor M3 begins to increase, allowing the voltage at HIZ node 302 to increase toward VBIAS. At time T8, reset signal RST achieves its maximum amplitude and output node 303 is completely discharged to the negative voltage supply. This causes transistor M3 to shut off completely, increasing the rate at which HIZ node 302 rises toward VBIAS. At time T9, HIZ node 302 achieves the voltage VBIAS.
There are disadvantages of the comparator design of FIG. 3. For example, VBIAS for high impedance node HIZ 302, must have just enough voltage to enable transistor M4 to sink one-half the current flowing through transistor M1 when transistor M2 is off. Otherwise, if the voltage at HIZ is too large, transistor M4 conducts more current and the circuit will be unbalanced. In other words, for transistor M2 to conduct enough current to begin charging up the output node, IN- will have to be higher than IN+ by an offset voltage determined by the VBIAS offset. If the voltage at HIZ is too low, then the current conducted through transistor M4 will be less and the comparator will begin to switch states when IN- is at a voltage higher than IN+ by a voltage offset determined by the voltage error at HIZ. The comparator is unbalanced if the proper voltage is not maintained.
Secondly, HIZ must be a very high impedance. In fact, to transistor M3, node HIZ must appear to be an open circuit. However, the voltage on HIZ must not drift while transistor M3 is off.
Thirdly, HIZ must have a low capacitance. If the capacitance at node HIZ is high, transistor M3 will take longer to pull HIZ low, thus reducing the effectiveness of the positive feedback in the circuit to shorten the rise time of the comparator output.
Further, the HIZ node must be isolated from signal noise. Since HIZ is a high impedance node, its susceptibility to noise pick-up is very high. Noise on HIZ also affects the offset of this comparator.
Generating the proper HIZ voltage (VBIAS) with a high output impedance and low capacitance, requires a significant amount of circuitry and consumes a significant amount of area on the integrated circuit chip. The HIZ node must also be isolated from noisy signals, thus adding additional constraints on the design.
One technique to minimize the effect of the comparator/latch delay is described in co-pending U.S. patent application Ser. No. 07/960,534, entitled "Linearized and Delay-Compensated All-CMOS VCO", and assigned to the present assignee. This technique utilizes the compensation loop illustrated in FIG. 1.
VCO core block 208 receives control current I on line 113 and clk+ and clk- signals. Outputs 229 and 230 of VCO core 208 are coupled to the positive voltage supply through capacitors 227 and 228. VCO core 208 operates in a similar manner to VCO core 202, thus generating voltage signals at output nodes 229 and 230, which mirror the voltages at nodes 217 and 218, respectively. Track-and-hold circuits 219 and 220 are coupled to output nodes 229 and 230 and also receive, as control signals, clk+ and clk- signals, respectively. These track-and-hold circuits track the voltage at the respective input nodes during the "track" operational state, and then hold the peak voltage value (ramp down minimum value), supplying this peak value to node 212 for the duration of the "hold" operational state. Due to switching circuitry within the track-and-hold circuits, circuits 219 and 220 are only coupled to node 212 while they are in their respective "hold" states. Node 212 provides the held peak value to the negative input of difference amplifier 211 through low-pass filter 210. The difference amplifier 211 compares the filtered peak values with an externally provided reference voltage 224 to generate the trip voltage signal on wire 225. Thus, a compensation loop is formed. The compensation loop alters the trip voltage in such a way that the voltage difference V between the positive voltage supply value and the trip voltage is decreased as the operating frequency increases. Thus, the voltage overshoot of the VCO core caused by the comparator/latch delay is compensated with a corresponding change in the trip voltage. The frequency response of this compensated circuit is: ##EQU2## where N is the gain of difference amplifier 211 and V' is the difference between the supply voltage value and the reference voltage. For a gain of N=10, the linear region of the compensated circuit can be increased by as much as a factor of 11 (depending on method of measurement). This greatly increases the range of the VCO. However, as the altered trip voltage rises closer to the voltage supply value, the noise immunity of the circuit is diminished. Thus, for higher frequency operation, this compensated circuit may experience phase jitter generated by noise from the voltage supply.